an-793 application note one technology way ? p.o. b ox 9106 ? n orwood , ma 02062-9106 ? t el : 781/329-4700 ? f ax : 781/461-3113 ? www.analog.com esd/latch-up considerations with i coupler ? isolation products by rich ghiorse introduction analog devices i coupler products offer an alternative iso - lation solution to optocouplers with superior integration, performance, and power consumption characteristics. an i coupler isolation channel consists of cmos input and output circuits and a chip scale transformer (see figure 1). because the i coupler employs cmos technology, it can be more vulnerable to latch-up or electrostatic discharge (esd) damage than an optocoupler when subjected to system-level esd, surge voltage, fast transient, or other overvoltage conditions. figure 1. adum140x quad isolator this application note provides guidance for avoiding these problems. examples are presented for various system-level test confgurations showing mechanisms that may impact performance. for each example recom - mended solutions are given. later this year, analog devices is introducing hardened versions of most i coupler products that will have improved immunity to latch-up and electrical overstress (eos). this new product family, the adum3xxx series, will be pin - compatible with the existing adum1xxx series products and will offer identical performance specifcations. both product families will continue to be made available. components vs. systems simply put, a component is a single integrated device with interconnects while a system is a nonintegrated device built from several interconnected components. in almost all cases the distinction between a component and a system is obvious. however, the differences between component and system tests may not be so obvious. further, component specifications may not directly indicate how a device will perform in system - level testing. esd testing is a good example of this. esd, surge, burst, and fast transient events are facts of life in electronic applications. these events generally consist of high voltage, short duration spikes applied directly or indirectly to a device. these events arise from interaction of the device to real-world phenomena, such as human contact, ac line perturbations, lightning strikes, or common-mode voltage differences between system grounds. component-level esd testing is most useful in deter - mining a devices robustness to handling by humans and automated assembly equipment prior and during assembly into a system. component-level esd data is less useful in determining a devices robustness within a system subjected to system-level esd events. there are two reasons for this. ? system - and component- level esd testing have different objectives. component-level testing seeks to address conditions typically endured during com - ponent handling and assembly. system-level testing seeks to address conditions typically endured during system operation. ? the specifc conditions a component is subjected to during system-level testing can be a strong func - tion of the board/module/system design in which it resides. for example, long inductive traces between a system and component ground can actually impose a more severe voltage transient onto a component than is imposed on the system at the test point. rev. 0
C2 C an-793 C3 C an-793 table i summarizes the esd test results for the adum140x quad isolator. one might conclude from table i that i couplers can only be used in systems with esd ratings of < 4 kv. in reality it is quite common for i couplers to be used in systems that pass 15 kv esd levels per iec 61000 - 4 -2. the difference is in the test methods: the component-level tests call for direct application of esd events to the pins or body of an unpowered device, while system-level tests call for application esd events to various locations in the system accessible to external esd occurrences. furthermore, the specifc waveforms used in component-level and system-level testing differ. table i. adum140x esd test results esd first pass first fail model voltage (v) voltage (v) human body model 3,500 4,000 field induced charge device model 1,500 2,000 machine model 200 400 for complete information on analog devices esd testing, refer to the analog devices reliability handbook . to accurately predict the performance of i couplers in a system, the designer needs to understand the nature of the system tests and weigh how they impact the i coupler at the component level. table ii lists common system-level tests used in i coupler applications. several examples of these tests will be discussed later. table ii. common system tests used in i coupler applications test test standard purpose voltage (v rms) 1 iec 61000-4-2 esd 2,000 to 15,000 iec 61000-4-4 fast transient/burst 500 to 4,000 iec 61000-4-5 surge 500 to 4,000 1 iec 61000-4 tests include compliance levels; the test voltages shown are the ranges for level 1 (lowest) through level 4 (highest) compliance. i coupler model for analyzing system test performance figure 2 shows a circuit model of an i coupler which is useful to understand the impact of system-level testing. inductors l1, l2, l3, and l4 are due largely to package pins and bond wires, while capacitor c1 is due to the stray capacitance across the isolation barrier. the induc - tance values are approximately 0.2 nh. the capacitance value is approximately 0.3 pf per i coupler channel. l1 v dd1 v in gnd 1 v dd2 v o gnd 2 l3 c1 l2 l4 figure 2. i coupler model useful in analyzing system designs latch-up in cmos devices inherent in a cmos process are parasitic pnp and npn transistors confgured as silicon control rectifers (scr). latch-up is a condition that comes about when this parasitic scr is triggered. this causes a low resis - tance to appear from v dd to ground, and a subsequent large current to be drawn through the device. this excessive current lays open the possibility of damage due to eos. damage caused by latch-up can range from complete destruction of the device to parametric degradation. more insidious are latent failures that could affect operation later in a systems lifetime. an excellent treatise on the subject of latch-up in general can be found in the analog dialogue 35 - 05 (2001) article, winning the battle against latch- up in cmos switches. while this article specifcally addresses problems with cmos switches, it is generally applicable to all cmos devices, including i couplers. the use of ceramic bypass capacitors to minimize supply noise between v dd and ground is highly recommended in all i coupler applications. these should have a value between 0.01 f and 0.1 f and be placed as close as possible to the i coupler device. even with adequate bypassing, latch-up problems may still occur in some applications. placing a 200 resistor in series with v dd is also helpful. this limits the supply current to 25 ma in 5 v applications, which is below the latch-up trigger current. however, depending on the supply current being drawn, this series resistance can reduce the supply voltage at the i coupler to an unacceptable level. this is most likely to be a concern when operating at high data rates that involve high supply currents. usually the mechanism that causes latch-up is an over - voltage condition beyond the parts absolute maximum rating (>7.0 v or C2 C an-793 C3 C an-793 iec 61000-4-2 esd testing a block diagram of the iec 61000- 4-2 esd test is shown in figure 3. in this test, esd contact or air discharges are applied at various points on a system chassis. this gives rise to several mechanisms that can cause latch- up problems for an i coupler. these include injected current via one of the i coupler grounds as well as inductive coupling from esd currents in the system chassis or in printed wiring board traces. system chassis chassis ground esd source esd zap to 15kv air or contact discharg e figure 3. iec 61000-4-2 esd test injected esd current the frst possible mechanism for latch- up is one in which excessive esd current is injected into an i coupler ground. figure 4 shows a situation where an i coupler is used as a foating output (the same mechanism can be present in a foating input confguration). in this instance the chassis impedance, z chassis , gives rise to an injected current during an esd discharge. this current fows in the loop formed by l3, c2, l4, and c stray . c stray is the capacitance from the shield of an output cable to chassis ground. the larger the value of c stray , the larger the injected current and the consequent internal noise voltage appearing across l4. if this voltage forces gnd 2 beyond its absolute maximum rating, then latch-up could occur. the following measures are recommended to avoid current injection diffculties: ? minimize the chassis impedance to ground. ? minimize c stray , the cross-isolation barrier capacitance. ? if possible place a 200 resistor in series with v dd2 to limit latch-up trigger current. ? place a 50 resistor between chassis ground and gnd 1 . this reduces i injected and ultimately v noise . ? place a transient absorbing zener diode from the connection to chassis ground. this clamps the noise voltage to within the zener voltage. inductive coupling from esd current one consideration is the possibility of inductive coupling from esd current present in the i coupler printed wiring board or system chassis. inductive pickup on i coupler transformers from external magnetic fields is not a problem in the vast majority of applications; however, there have been rare instances in iec 61000 - 4 -2 esd testing where this phenomenon has been noted. solutions to this problem are straightforward. v dd2 d out gnd 2 v dd1 d in gnd 1 l3 l4 c2 200 50 c stray +v noise C minimize size of c stray , coupling from output cable shield to chassis ground use 50 resistor to decrease i injected addition of transient absorber to clam p noise voltage at gnd 1 pin chassis/earth ground 200 resistor to limit latch-up trigger current v logic i injected z chassis esd zap figure 4. injected esd current mechanism and recommended solutions rev. 0 rev. 0
C4 C an-793 C5 C an-793 figure 5 shows an esd test setup and the paths of cur - rents i esd and i 1 caused by an esd strike. these currents can be very large, and induce large magnetic felds on the application printed wiring board and chassis. the placement and geometry of ground traces, ground circuit connections, board location, and orientation within the chassis are all critical in minimizing inductive pickup from the radiated magnetic felds. figure 5a shows a poor layout which uses a thin ground trace near the i coupler. it also shows a ground loop that allows some of i esd to fow through the board ground circuit as i 1 . close proximity and narrow trace widths increase the magnitude of the induced magnetic feld. if strong enough, this can cause i coupler latch-up as discussed above. figure 5b shows an optimal design using a wide ground plane further away from the i coupler and a single point ground which prevents i esd from flowing in the board ground circuit. when designing ground circuits, it is always helpful to think in terms of current paths. when designing the chassis for the system, it is impor - tant to minimize impedance of the chassis ground con - nection. it is also helpful to mount printed circuit boards as far away from the edge of the chassis as possible, and to have the board oriented so that i couplers are parallel to any radiated magnetic felds as depicted in figure 6. poor ground layout figure 5a application board i coupler system chassis esd zap point i 1 i 2 i esd poor ground technique: 1. ground loop allows part of the lesd to flow through board ground 2. thin ground conductor will radiate magnetic field and cause pickup in i coupler transformers good ground layout figure 5b application board i coupler system chassis esd zap point i 1 i esd good ground technique: 1. use of wide ground plane lowers inductance and will lower noise 2. no loop so lesd flows through the chassis only ground plane figure 5. contrasting examples of board ground circuits best orientation pc board i coupler packag e chip scale transformer magnetic field orientation parallel to transformer windings minimizes v induced + v induced C worst orientation i coupler package magnetic field orientation right angle to transformer windings maximizes v induced chip scale transformer v dd figure 6. external magnetic field interaction with i coupler tranformers if inductive coupling is a problem, recommended solu - tions include the following: ? properly design ground system to avoid ground loops. ? use ground plane instead of single narrow traces. ? orient print wiring boards away from chassis boundaries. ? if possible, orient the i coupler parallel to external magnetic felds as depicted in figure 6. iec 61000-4-5 surge testing surge testing per iec 61000 - 4 -5 is another common system - level test in industrial and instrumentation applications. figure 7 depicts an i coupler in a surge test confguration showing associated bypass and stray capacitances. v test is the surge test voltage appearing between earth ground and the boards local ground gnd 1 . this test typically has test voltages up to 4 kv. as shown in figure 7, if excessive stray capacitance exists across the isolation barrier, the voltage at v dd1 can be driven above its absolute maximum rating and damage the i coupler. rev. 0 rev. 0
C4 C an-793 C5 C an-793 ?? ? ??? ? ?? ??? ? ? ??? ? ? ??? ? ??? ? ??? ? ?? ?? ?? ?? ? ???? ?? ?? ?? figure 7. i coupler in iec 61000-4-5 surge test setup figure 8 shows the model reduced for easier analysis of circuit. the simplifed schematic ignores negligible effects of lead inductances and lumps c stray as a com - puted element (equation 1). ? ??? ? ??? i ??????? ??? ? ? ? ? ????? ? ???? ??? ? ??? ? ? ? ??????????? ??????????? ? ??? ??????? ? ????? ?????????????? ????????? ???????? ??????? ? ??? ? ? ? figure 8. simplifed equivalent circuit of figure 7 using figure 8, and ignoring inductances, c stray is given as c c 4 c c 5 c c 5 stray bp2 bp2 = + + (1) the coupled voltage v x is calculated using a simple capacitor divider v v c c c x test stray stray bp1 = + (2) equation 2 shows that making c stray small compared to c bp1 can minimize v x . for example, with a test voltage of 4 kv and a bypass capacitance of 0.01 m f, even the moderate amount of 10 pf of stray capacitance would create a coupled v dd1 voltage of 4 v. when imposed on top of the normal supply voltage, this would induce latch-up. in such a situation the bypass capacitance c bp1 should be increased to 0.1 m f to reduce the coupled voltage to 0.4 va much safer value. do the following for best results: ? minimize capacitances between i coupler foating grounds and system grounds. ? provide adequate bypassing with good quality ceramic bypass capacitors with values large enough to minimize the induc ed voltage at i coupler supply pins. ? ensure v dd1 and v dd2 are free from noise spikes. ? if possible add a 200 v resistor in series with v dd1 to limit parasitic scr trigger current. ? use a transient-absorbing zener diode across v dd1 . iec 61000-4-4 fast transient and burst testing example fast transient and burst testing per iec 61000 - 4 - 4 is another common system - level test that can cause problems if good design practice is not followed. this test couples high voltage fast edge signals onto system ac mains. c stray transformer winding capacitance coupled transient noise through c stray to v dd1 or v dd2 coupled transient noise onto ac line recommended solution transient absorber coupling network eft/burst generator board with coupler ac lines system power supplies v dd1 v dd2 figure 9. iec 61000-4-4 fast transient/burst test setup figure 9 shows a simplifed circuit diagram of a fast transient test setup. the main mechanism for problems here is interwinding capacitance of the system power supplies transformers. this stray capacitance can couple fast transient signals from the ac mains to the i coupler supply pins. if the voltage impressed on the i coupler supplies is high enough, then maximum rated supply voltages can be exceeded and latch-up is possible. the best preventive measures in this example are: ? use low interwinding capacitance supplies. ? minimize supply noise by using adequate bypassing. ? use zener diode clamps across the i coupler supplies to clamp noise voltages. rev. 0 rev. 0
C6 C an-793 C7 C new esd-hardened i couplers to better support the use of i couplers in harsh esd applications, analog devices is introducing a new line of i coupler products. the adum3xxx series takes advantage of improved circuit designs and layouts to increase i coupler robustness to esd events. these new products are pin- and specifcation- compatible with their adum1xxx series counterparts. for many installed applications, the standard i coupler products work just fne. therefore, both the standard adum1xxx and the esd-hardened adum3xxx series will continue to be offered. the part numbering for the adum3xxx series is analogous to that of the standard product except that only pb-free models are provided. table iii gives examples of the part numbering for the two product families. table iii. part numbering examples for various standard and esd-hardened i coupler products standard esd-hardened products products adum1100arwz adum3100arwz adum1201arwz ADUM3201ARWZ adum1301brwz adum3301brwz adum1402crwz adum3402crwz inside the adum3xxx series i coupler several design enhancements are incorporated into the adum3xxx series i couplers to create a more robust device. specifc improvements include: ? esd protection cells added to all input/output inter - faces. ? key metal trace resistances reduced using wider geometry and paralleling of lines with vias. ? the scr effect inherent in cmos devices minimized by use of guarding and isolation techniques between pmos and nmos devices. ? areas of high electric feld concentration eliminated using 45 corners; on metal traces. ? supply pin overvoltage prevented with larger esd clamps between each supply pin and its respective ground. conclusion by following the guidelines set forth in this application note, designers can be assured of success in their application of i couplers at the system level. problems with system-level tests can be anticipated using the lumped-element circuit model presented for the i coupler. with this model and a good understanding of the various system tests, designers can avoid problems by employing the preventive techniques suggested in this document. in situations where the recommendations cannot be implemented due to cost, system design, or other considerations, the new adum3xxx i coupler provides an alternative method of avoiding esd/latch-up problems. rev. 0
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an05547C0C7/05(0) C8 C ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners.
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